Digital phase-locked loops (DPLLs) are becoming attractive as replacements for analog PLLs in frequency synthesizers due to their technology portability, loop bandwidth configurability, and overall silicon area consumption. Moreover, among frequency synthesizers, those capable of fractional-N multiplication are preferred due to relaxed system level planning, such as input reference frequency and synthesized output frequency. However, several issues regarding quantization noise and non-linearity, which leads to spurious generation, limit the use of DPLLs in various applications.
On issue with fractional operation is when near-integer channels are desired, where unfiltered spurious tones can fall within the PLL loop bandwidth. The source of the more significant spurious tones is in the phase detector. Historically, in a DPLL, the fractional phase detector is implemented by a time-to-digital converter (TDC) that is capable of quantizing the phase difference between the input and output signals by inverter elements (delay). The limited resolution and non-linearity of the inverter elements in the TDC can produce prohibiting spurious tones.
Recently, the resolution of the phase detection has been improved by the use of a digital-to-time converter (DTC) that delays one of the signals (either input or output frequency) with much more accuracy. However, a conventional DTC is applied to only one of the signals, requiring the use of very complex calibration logic with potential large area and power consumption to avoid spurious tone generation. Even then, noise on the power supply and dynamic mismatches cannot be calibrated easily and very often the phase measurement results are worse than simulated.